PhD in Optimization of Micropillar Microfabrication for Fan-Out Wafer Level Packaging
Develop advanced microfabrication processes for ultra-fine pitch microbumps in heterogeneous multichip integration.
Best for:Best for materials engineering or microelectronics PhD candidates with strong microfabrication and cleanroom experience, seeking to advance heterogeneous integration technologies.
Overview
This PhD position at Université de Sherbrooke focuses on advancing microelectronic packaging by optimizing the fabrication of high-density vertical interconnections (pitch < 30 µm) for flip-chip die-to-wafer (D2W) assembly. The project addresses critical challenges in thermomechanical strength, electromigration resistance, and warpage control in advanced Fan-Out Wafer Level Packaging (FOWLP). Under the supervision of Professor Dominique Drouin, the candidate will conduct research at the Interdisciplinary Institute for Technological Innovation (3IT) and the MiQro Innovation Collaborative Center (C2MI). The work involves microfabrication process optimization, electroplating, thermocompression bonding, and morphological characterization of micropillars. The successful candidate will contribute to developing compliant interconnects that enhance the integrity of advanced microelectronic systems, supported by an interdisciplinary research environment combining academic and industry expertise.
What you'll do
- Conduct a literature review on microbump fabrication, focusing on ultra-fine pitch Cu/Ag/Sn micropillars.
- Optimize microfabrication processes in the cleanroom, including lithography, alignment, and exposure techniques.
- Develop and refine electroplating parameters to create fine-pitch micropillars with high uniformity.
- Design and test thermocompression bonding (TCB-D2W) process conditions tailored to micropillar structures.
- Perform comprehensive morphological characterizations to analyze micropillar uniformity and quality across wafer sections.
- Collaborate with industry partners as part of the IBM/NSERC Alliance Project on Multi-Chip Heterogeneous Integration.
Requirements
Degree required: Master's degree or equivalent in Engineering (Mechanical, Electrical, or Materials) or a related field
Degree offered: PhD
Language: English; good proficiency required
Instruction: English
- Experience with microfabrication processes in cleanroom environments
- Familiarity with lithography, alignment, and exposure techniques
- Knowledge of electroplating and thin-film deposition methods
- Proficiency in morphological characterization techniques (e.g., SEM, AFM)
- Basic understanding of thermomechanical bonding processes
- No specific nationality or residency restrictions mentioned
- No age or prior experience caps specified
Funding & terms
How to apply
Deadline: 2026-12-30 (America/Toronto)
Applicants must send an email to inpaqt@usherbrooke.ca with the subject line 'PhD-Optimization of Micropillar Microfabrication Process for Fan-Out Wafer Level Packaging'. Include a cover letter, CV, and any relevant academic transcripts or research statements. No formal application portal is required.
- Cover letter
- CV
- Master's degree transcripts
- Research statement (if applicable)
Contact
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