Junction defect characterization of low thermal budget SOI MOSFET

This PhD position is hosted jointly at CEA-Leti and CROMA under the supervision of Daphnée Bosch. The research focuses on analyzing the junction defects of novel transistors fabricated under restricted thermal budgets for 3D sequential integration. The candidate will engage in simulation, process understanding, cleanroom integration management, and extensive physical and electrical characterization. The findings will be disseminated through presentations and peer-reviewed articles.

• Conduct literature reviews, simulations, and TCAD modeling to conceptualize junction structures.
• Investigate process steps including ion implantation and solid-phase epitaxial regrowth.
• Manage integration and cleanroom fabrication workflows.
• Perform physical and electrical characterizations such as noise measurements and Deep-Level Transient Spectroscopy.
• Valorize research findings through scientific presentations and journal publications.