AI Model Deployment Using Hardware-Aware On-Chip Fine Tuning

This PhD position at Universite Grenoble Alpes focuses on creating hardware-algorithm co-design solutions to address variability and mismatches in emerging unconventional hardware for Edge-AI applications. Working within the Laboratory for Intelligent Integrated Circuit Design for Image within the Optics Department (LETI), the candidate will research inference-level self-calibration strategies that avoid fully supervised on-chip retraining. The project involves studying adaptation methods, defining relevant Edge-AI use cases, and validating generic fine-tuning techniques through electrical simulations and potentially custom ASIC hardware setups. The successful candidate is expected to conduct rigorous independent research and contribute to advancements in hardware-aware artificial intelligence.

• Investigate and evaluate existing adaptation strategies including weight-based, feature-based, output-based, and domain adaptation methods.
• Design and develop task-agnostic, inference-level self-calibration techniques to compensate for hardware mismatches.
• Formulate relevant Edge-AI application scenarios and implement generic fine-tuning algorithms.
• Perform low-level electrical simulations to test and validate proposed algorithms.
• Collaborate on experimental testing of developed algorithms using custom ASIC-based hardware setups where applicable.