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Microelectronics and Nanotechnology● OpenPreview

Modeling and characterization of CFET transistors for enhanced electrical performance

Study and optimize strain engineering in next-generation CFET transistors through numerical modeling and advanced microscopy.

Best for:Best for graduate students with a strong background in semiconductor physics, numerical modeling, and materials characterization.

UNIVERSITE GRENOBLE ALPES · Grenoble, France · R1 · First-stage researcher
More professors at UNIVERSITE GRENOBLE ALPES
semiconductor devicesnumerical modelingstrain engineeringtransmission electron microscopyCMOS technology
Deadline
Nov 30, 2026
46 days
Funding
Salaried
CEA contract
Start date
2026-10-01
Fixed-term
Location
Grenoble
France

Overview

This PhD position at Université Grenoble Alpes, conducted within the Silicon Components Department (LETI), focuses on investigating Complementary Field Effect Transistors (CFETs) to advance transistor miniaturization for high-performance computing. The research involves studying and optimizing channel strain engineering to improve carrier mobility and overall device electrical performance. The candidate will combine finite element numerical modeling of technological processes with experimental characterization using transmission electron microscopy coupled with precession electron diffraction (TEM-PED). Ultimately, the work aims to develop dedicated modeling tools and robust characterization methodologies to better understand strain mechanisms in stacked CMOS architectures.

CFETtransistor miniaturizationcarrier mobilityfinite element methodsTEM-PEDsilicon componentsepitaxy

What you'll do

  • Perform numerical modeling of technological processes using finite element methods to predict strain distributions in CFET structures
  • Conduct experimental characterization of crystalline deformation using transmission electron microscopy coupled with precession electron diffraction (TEM-PED)
  • Analyze and quantify strain fields in transistor channels and compare experimental results with simulation outputs
  • Account for complex technological stacks and critical fabrication steps such as epitaxy within modeling frameworks
  • Contribute to the development of dedicated simulation tools and advanced characterization methodologies for next-generation transistors

Requirements

Degree required: Master's degree or equivalent in Physics, Materials Science, Microelectronics, or related field

Degree offered: PhD

Language: English or French proficiency as per institutional standards

Instruction: English / French

Required skills
  • Background in semiconductor physics and transistor operation
  • Experience with numerical modeling or finite element methods
  • Familiarity with materials characterization techniques
  • Strong analytical and problem-solving skills
Nice to have
Prior experience with transmission electron microscopy (TEM)Knowledge of strain engineering in semiconductor materialsFamiliarity with cleanroom fabrication processes or epitaxy

Funding & terms

Type
Salaried
Amount
CEA contract
Duration
36 months
Programme
CEA
CEA

How to apply

Deadline: 2026-11-30

Interested candidates should submit their application through the official doctoral portal before the stated deadline. Ensure all required academic transcripts and supporting documents are attached to the submission.

Documents required
  • CV
  • Cover letter
  • Academic transcripts
↗Apply on site

Contact

Sylvie Jarjayes· Supervisor

sylvie.jarjayes@cea.fr

04.38.78.46.68

SJ
Prof.
Sylvie Jarjayes
Département Composants Silicium
Lab
Laboratoire de Simulation et Modélisation
UNIVERSITE GRENOBLE ALPES
France
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