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Quantum Physics and Microelectronics● OpenPreview

PhD Position: 3D Interconnects for Quantum Processor Units

Develop advanced 3D integration technologies to scale quantum processors and improve their performance.

Best for:Best for candidates with a strong background in physics, materials science, or microelectronics interested in quantum hardware.

Université Grenoble Alpes · Grenoble, France · R1 · First-stage researcher
More professors at Université Grenoble Alpes
Quantum Computing3D IntegrationMicroelectronicsRadiofrequency CharacterizationSuperconducting Devices
Deadline
Nov 30, 2026
46 days
Funding
Salaried
CEA
Start date
2026-10-01
Fixed-term
Location
Grenoble
France

Overview

This PhD position at Université Grenoble Alpes, hosted within the CEA-LETI laboratory, focuses on developing 3D interconnect technologies for next-generation quantum processors. The research aims to address critical scaling challenges by utilizing techniques such as flip-chip bonding, multi-layer wiring, and through-silicon vias (TSV). The successful candidate will work at the intersection of materials science, technology, and physics to characterize the electrical and radiofrequency properties of these interconnects. The role involves designing test vehicles, managing fabrication processes, and conducting low-temperature measurements to assess their impact on quantum device performance.

Quantum ProcessorTSVFlip-chip bondingCryogenic measurementsCEA-LETIQuantum hardware

What you'll do

  • Design and layout of test vehicles for 3D quantum interconnects.
  • Manage the fabrication process of quantum device test structures.
  • Conduct low-temperature electrical and radiofrequency characterization of samples.
  • Perform detailed data analysis to evaluate the impact of 3D integration on quantum properties.
  • Write technical reports and contribute to scientific publications.

Requirements

Degree required: Master's degree in Physics, Microelectronics, or Materials Science

Degree offered: PhD

Language: English proficiency is expected for research communication.

Instruction: English

Required skills
  • Knowledge of semiconductor fabrication processes
  • Experience with electrical or radiofrequency characterization
  • Ability to work in a collaborative research environment
  • Strong analytical and technical writing skills
Nice to have
Experience with low-temperature measurement setupsFamiliarity with quantum computing hardware architecturesExperience with CAD tools for layout design
Eligibility
  • Must hold a Master's degree or equivalent by the start date.

Funding & terms

Type
Salaried
Amount
CEA
Duration
36 months
Programme
CEA
CEA

How to apply

Deadline: 2026-11-30

Interested candidates should contact the supervisor via email with their application materials. Ensure all required documents are included to be considered for the position.

Documents required
  • CV
  • Cover letter
  • Academic transcripts
✉Apply by email

Contact

Candice Thomas· Supervisor

candice.thomas@cea.fr

0438782575

CT
Prof.
Candice Thomas
Département Composants Silicium (LETI)
Lab
Laboratoire des Technologies d'Intégration 3D
Université Grenoble Alpes
France
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