FeFET-Based In-Memory Computing for Low-Power Edge AI

The Université de Sherbrooke invites applications for a graduate research position focusing on FeFET-based in-memory computing architectures to support energy-efficient edge artificial intelligence. Operating within the Interdisciplinary Institute for Technological Innovation (3IT), the selected researcher will work on designing, modeling, simulating, and experimentally validating hardware solutions that overcome traditional memory-bottleneck limitations. The project involves developing SPICE or Verilog-A models, designing memory cells and MAC arrays, and testing fabricated integrated circuits. The successful candidate will collaborate closely with academic and industrial partners to evaluate architecture performance.

• Define CNN hardware architectures, weight representations, and efficient layer mappings onto FeFET arrays.
• Develop SPICE or Verilog-A models for FeFET devices that incorporate analog programming and non-idealities.
• Design memory cells, multiply-accumulate arrays, and essential peripheral circuits for programming, readout, and accumulation.
• Simulate circuit performance metrics including accuracy, energy consumption, latency, throughput, and silicon area under realistic variability conditions.
• Prepare multi-project wafer test blocks, establish measurement setups, and characterize fabricated integrated circuits.
• Execute convolutional neural networks using empirical measurement data and compare results against simulation baselines and digital references.