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Photonics● OpenPreview

Electrical characterization and optimization of III-V HBT on Si for 6G and datacom applications

Develop high-performance InP-based HBTs on silicon to enable next-generation 6G and AI datacenter communications.

Best for:Best for candidates with a strong background in semiconductor physics, RF characterization, and device modeling.

CEA · France · R1 · First-stage researcher
More professors at CEA
Semiconductor PhysicsRF EngineeringHeterojunction Bipolar Transistors6G CommunicationsOptical CommunicationsDevice Modeling
Deadline
Nov 30, 2026
46 days
Funding
Salaried
CEA
Start date
2026-10-01
Fixed-term
Location
France
on-site

Overview

This PhD position at the Laboratoire des Transistors Avancés (LETI) focuses on the development of InP-based Heterojunction Bipolar Transistors (HBTs) integrated on silicon substrates. The research aims to overcome current silicon technology limitations for Sub-THz frequency power amplifiers and high-speed optical drivers in AI datacenters. The successful candidate will perform electrical characterization, simulate device parasitics, and collaborate with process engineers to optimize device architecture. This role is essential for advancing high-speed, energy-efficient communication technologies.

InP on SiliconSub-THzRF CharacterizationPower AmplifiersCMOS IntegrationDevice Optimization

What you'll do

  • Conduct comprehensive electrical characterization of various device geometries and technological splits.
  • Perform DC and RF measurements including IV curves, thermal analysis, S-parameters, and Load-Pull.
  • Develop simulations to analyze key parasitics and evaluate new device architectures.
  • Collaborate with process engineers to correlate electrical performance with fabrication parameters.
  • Contribute to the optimization of device architecture to enhance RF performance and thermal management.

Requirements

Degree required: Master's degree in Electrical Engineering, Physics, or a related field.

Degree offered: PhD

Language: English proficiency required for research and reporting.

Instruction: English

Required skills
  • Strong understanding of semiconductor device physics.
  • Experience with RF measurement techniques and equipment.
  • Proficiency in device simulation and modeling tools.
  • Ability to work in a collaborative, multidisciplinary research environment.
Nice to have
Experience with III-V semiconductor materials.Knowledge of CMOS-compatible fabrication processes.Familiarity with thermal analysis of electronic devices.

Funding & terms

Type
Salaried
Amount
CEA
Duration
36 months
Programme
CEA
CEA

How to apply

Deadline: 2026-11-30

Interested candidates should contact the supervisor via email with their application materials. Ensure all required documents are prepared for submission.

Documents required
  • CV
  • Cover letter
  • Academic transcripts
✉Apply by email

Contact

Alexis Divay· Supervisor

alexis.divay@cea.fr

04.38.78.47.52

AD
Prof.
Alexis Divay
Département Composants Silicium (LETI)
Lab
Laboratoire des Transistors Avancés
CEA
France
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