Implementation of TFHE on RISC-V Based Embedded Systems

This PhD position at Université Paris-Saclay, hosted within the CEA laboratory, focuses on accelerating Fully Homomorphic Encryption (FHE) to enable secure computations directly on encrypted data. The project targets the lightweight TFHE scheme, aiming to dramatically reduce bootstrapping latency on RISC-V-based embedded systems. The successful candidate will design hardware accelerators, explore cryptographic synergies, and investigate instruction set architecture (ISA) extensions. The expected outcome is a functional, optimized prototype bridging advanced cryptography and low-power hardware design.

• Design and prototype innovative implementations of the TFHE scheme on RISC-V-based systems
• Analyze and minimize performance bottlenecks associated with the bootstrapping operation
• Explore hardware acceleration synergies between post-quantum cryptography and TFHE
• Develop tightly coupled acceleration approaches integrating RISC-V cores and dedicated hardware
• Investigate the integration of fully homomorphic computation domains within processor instruction set architectures