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PhD Position in Advanced SOI Technologies: Design, Integration & Electrical Characterization

Join CEA-Leti to develop innovative localized ground plane modules for advanced semiconductor applications.

Best for:Best for candidates with a strong background in semiconductor physics, device integration, and cleanroom fabrication.

Université Grenoble Alpes, Grenoble INP · Grenoble, France · R1 · First-stage researcher
More professors at Université Grenoble Alpes, Grenoble INP
Semiconductor DevicesFDSOI TechnologyRF DevicesDevice IntegrationCleanroom FabricationElectrical Characterization
Deadline
Dec 31, 2026
77 days
Funding
Salaried
CEA
Start date
2026-11-01
Fixed-term
Location
Grenoble
France

Overview

This PhD position at CEA-Leti focuses on the development and electrical characterization of a technological module featuring a localized ground plane. The research aims to support diverse applications including EU FDSOI, RF devices, ultra-miniaturized pixels, and cryo-RF/quantum technologies. The successful candidate will manage the entire lifecycle of the module, from initial simulation and bibliography to cleanroom fabrication and final electrical testing. You will be supported by a team of experts throughout the design, integration, and characterization phases of the project.

SOISilicon-on-InsulatorCEA-LetiMicroelectronicsSemiconductor PhysicsDevice DesignCleanroom

What you'll do

  • Conduct literature reviews and perform device simulations to guide module design.
  • Manage the integration and fabrication processes within a cleanroom environment.
  • Perform physical and electrical characterization, including mobility and interface trap analysis.
  • Analyze existing experimental data to support ongoing research objectives.
  • Present research findings at scientific conferences and contribute to peer-reviewed publications.

Requirements

Degree required: Master's degree in Microelectronics, Physics, or a related engineering field.

Degree offered: PhD

Language: English proficiency is expected for research communication; French is not strictly required.

Instruction: English

Required skills
  • Strong understanding of semiconductor device physics.
  • Experience with cleanroom fabrication processes.
  • Proficiency in electrical characterization techniques.
  • Ability to perform device simulation and data analysis.
Nice to have
Knowledge of SOI (Silicon-on-Insulator) technologies.Familiarity with RF device design or quantum technology applications.Experience with material characterization methods like CMP or bonding.

Funding & terms

Type
Salaried
Amount
CEA
Duration
36 months
Programme
CEA
CEA

How to apply

Deadline: 2026-12-31

Interested candidates should contact the supervisor via email with their application materials. Ensure all relevant academic documents are included to support your candidacy.

Documents required
  • CV
  • Cover letter
  • Academic transcripts
✉Apply by email

Contact

Daphnée Bosch· Supervisor

daphnee.bosch2@cea.fr

0438789795

DB
Prof.
Daphnée Bosch
Département Composants Silicium (LETI)
Lab
Laboratoire des Transistors Avancés
Université Grenoble Alpes, Grenoble INP
France
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