PhD Position in 3D Ferroelectric Memories (FeRAM) with BEOL-Integrated Bitcells

This PhD position focuses on developing next-generation three-dimensional ferroelectric memories (FeRAM) using fully back-end-of-line (BEOL) integrated bitcells. Based at Université Grenoble Alpes and the CEA-Leti laboratory, the research will evaluate vertical amorphous oxide semiconductor field-effect transistors (AOSFETs) as alternative selectors for very low-voltage memory operation. The project centers primarily on Design Technology Co-Optimization (DTCO) to formulate dense bitcell integration schemes supported by recent experimental results. The candidate will work closely with leading researchers to contribute toward initial silicon demonstrations.

• Investigate and evaluate vertical amorphous oxide semiconductor field-effect transistors for advanced back-end-of-line FeRAM memory arrays
• Perform Design Technology Co-Optimization (DTCO) to design dense bitcells using realistic integration schemes
• Analyze electrical characteristics of back-end transistors to achieve low-voltage operation under 1V
• Incorporate recent experimental findings from CEA on AOSFETs and 3D ferroelectric capacitors into architectural models
• Contribute to simulation, layout, and preparation for initial silicon demonstrations