PhD on Predictable and High-Performance Processor Architectures

This doctoral position at Université Paris-Saclay, hosted within the LIST department, focuses on designing specialized hardware and software solutions for critical systems. The research investigates how to adapt high-performance in-order processor variants like CVA6 to meet strict timing guarantees without sacrificing throughput. The candidate will define general predictability schemes for speculative execution, addressing storage organization and rollback behaviors. Successful completion of the project requires rigorous investigation into computer architecture design and hardware-software integration.

• Develop and adapt high-performance variants of in-order processors such as CVA6.
• Design top-down techniques to introduce determinism and timing guarantees into processor pipelines.
• Investigate the tradeoff between execution predictability and raw hardware performance.
• Define general predictability schemes covering storage organization, caching, and resource arbitration.
• Implement and evaluate control mechanisms for speculative execution and rollback behavior.