PhD in Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems
Develop advanced shared-memory architectures for scalable and predictable multi-die chiplet performance.
Best for:Best for candidates with a strong background in computer architecture, chiplet design, and cache coherence protocols.
Overview
This PhD position at imec focuses on the design and optimization of Quality-of-Service (QoS) aware architectures for shared-memory chiplets within multi-die systems. The successful candidate will work on developing solutions that ensure scalable and predictable performance in complex heterogeneous computing environments. The research involves a combination of architectural design, simulation, and RTL implementation. Applicants are expected to contribute to the advancement of chiplet-based system design through rigorous technical research.
What you'll do
- Design and evaluate QoS-aware architectures for shared-memory chiplet systems.
- Develop and implement architectural models using simulation tools.
- Perform RTL design and verification for proposed architectural components.
- Analyze system performance and scalability in multi-die configurations.
- Document research findings and contribute to academic publications.
Requirements
Degree required: MSc in Electrical Engineering, Computer Science, or a related field.
Degree offered: PhD
Language: English proficiency required.
Instruction: English
- Strong understanding of computer architecture principles.
- Experience with chiplet-based system design.
- Proficiency in cache coherence protocols.
- Experience with hardware simulation and RTL design.
Funding & terms
How to apply
Deadline: N/A
Interested candidates should submit their application materials directly through the provided portal. Ensure all required academic and professional documentation is included for review.
- CV
- Academic transcripts
- Cover letter
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